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    Verilog/SystemVerilog/VHDL tutorial
    
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    Introduction
    
    Clone the project Clone the project
    Table of contents
    
    Change the directory
    
    Source the env variables
    
    Write your Verilog code
    
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    Design: 🕸️ Network-on-Chip
    Design: 🕸️ Network-on-Chip
    
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    Standalone RTL design
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    1. Create a project
    
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    Simple SoC
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    2. Port to SDK
    
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    LIF neuron on MicroZed
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  - Spiking Neural Network
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    Spiking Jelly
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    1.3 Input size and net reset
    
    3.1 Revisit LIF neuron
    
    3.2 Revisit LIF neuron part 2
    
    3.3 Design your neuron
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Table of contents

Change the directory

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