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Writing Verilog

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  - Verilog/SystemVerilog/VHDL tutorial
    Verilog/SystemVerilog/VHDL tutorial
    
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  - Simulate with Modelsim
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    Introduction
    
    Clone the project
    
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    Write your Verilog code
    
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  - ASIC
    ASIC
    
    Basic
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    Writing Verilog Writing Verilog
    Table of contents
    
    Verilog Coding Guidelines
    
    Wire/register/inout declarations follow this rule:
    
    Important notes
    
    RTL Simulation
    
    Synthesis (Synopsys DC)
    
    Place and Route
    
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    Design: 🕸️ Network-on-Chip
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    0. Installation
    
    Standalone RTL design
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    1. Create a project
    
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    3. Understand the reports
    
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    LIF neuron on MicroZed
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  - Spiking Neural Network
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    Neuron
    
    Izhikevich
    
    SNNTorch
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    Official tutorial
    
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    Spiking Jelly
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    1.1 Time-step
    
    1.2 Using neuron
    
    1.3 Input size and net reset
    
    3.1 Revisit LIF neuron
    
    3.2 Revisit LIF neuron part 2
    
    3.3 Design your neuron
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Table of contents

Verilog Coding Guidelines
- Wire/register/inout declarations follow this rule:
- Important notes

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