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Writing Verilog

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  - Verilog/SystemVerilog/VHDL tutorial
    Verilog/SystemVerilog/VHDL tutorial
    
    Intro
    
    Combinational Logic
    
    Sequential Logic
    
    Reset and Clock
    
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    Asic-world
    
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  - Simulate with Modelsim
    Simulate with Modelsim
    
    Introduction
    
    Clone the project
    
    Source the env variables
    
    Write your Verilog code
    
    Open Modelsim
    
    Use command line
    
    Code Coverage
    
    Write a script
    
    Learn More!
  - ASIC
    ASIC
    
    Basic
    Basic
    
    Getting started
    
    Writing Verilog Writing Verilog
    Table of contents
    
    Verilog Coding Guidelines
    
    Wire/register/inout declarations follow this rule:
    
    Important notes
    
    RTL Simulation
    
    Synthesis (Synopsys DC)
    
    Place and Route
    
    Mini Ex
    
    Advanced
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    Getting started
    
    Explore the library
    
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    Post-synthesis simulation with timing
    
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    OpenRAM
    
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    Design: 🕸️ Network-on-Chip
    Design: 🕸️ Network-on-Chip
    
    Getting started
    
    Simulation
    
    SNN Simulation
    
    Synthesis
    
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    Place and Route
    
    Power estimation
    
    Sample projects
  - FPGA
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    Basic
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    0. Installation
    
    Standalone RTL design
    Standalone RTL design
    
    1. Create a project
    
    2. Run the project on FPGA
    
    3. Understand the reports
    
    Simple SoC
    Simple SoC
    
    1. Create a project
    
    2. Port to SDK
    
    3. Run the program in the FPGA
    
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    SNN on Basys 3
    
    SNN on Arty 7
    
    LIF neuron on MicroZed
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  - Spiking Neural Network
    Spiking Neural Network
    
    Introduction
    
    Neurons
    
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    Neuron
    
    Izhikevich
    
    SNNTorch
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    Official tutorial
    
    Bindsnet
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    STDP learning
    
    Spiking Jelly
    Spiking Jelly
    
    1.1 Time-step
    
    1.2 Using neuron
    
    1.3 Input size and net reset
    
    3.1 Revisit LIF neuron
    
    3.2 Revisit LIF neuron part 2
    
    3.3 Design your neuron
- Accessing servers
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- 🎯 Optimization
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    Single Objective
    
    0-1 Knapsack
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    0-1 Knapsack
    
    MOO minicourse
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Table of contents

Verilog Coding Guidelines
- Wire/register/inout declarations follow this rule:
- Important notes

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