E3Computing's Docs

Writing Verilog

👾 E3Computing HP
🏠 Docs
ℹ️ Information
ℹ️ Information
- 🌐 About this website
- 🔰 Guidance for new student (AY 2026)
- 🔰 Checklist for new student orientation meeting
  🔰 Checklist for new student orientation meeting
- 🚂 Training for new members
  🚂 Training for new members
- 🔬 Server/Page Info
  🔬 Server/Page Info
- 📑 Paper submission
  📑 Paper submission
- 🎓 Graduation Thesis
  🎓 Graduation Thesis
  - Preparation
  - After the presentation
👨‍🏫 Invited Talks
👨‍🏫 Invited Talks
📅 Meetings
📅 Meetings
🗂️ Tutorial
🗂️ Tutorial
- List of tutorials
- 🛠 HW Design
  🛠 HW Design
  - Verilog/SystemVerilog/VHDL tutorial
    Verilog/SystemVerilog/VHDL tutorial
    
    Intro
    
    Combinational Logic
    
    Sequential Logic
    
    Reset and Clock
    
    Naming
    
    RTL template
    
    Testbench template
    
    Useful website
    Useful website
    
    Asic-world
    
    Stitt-hub
    
    RTL-Training Repo
  - Simulate with Modelsim
    Simulate with Modelsim
    
    Introduction
    
    Clone the project
    
    Source the env variables
    
    Write your Verilog code
    
    Open Modelsim
    
    Use command line
    
    Code Coverage
    
    Write a script
    
    Learn More!
  - ASIC
    ASIC
    
    Basic
    Basic
    
    Getting started
    
    Writing Verilog Writing Verilog
    Table of contents
    
    Verilog Coding Guidelines
    
    Wire/register/inout declarations follow this rule:
    
    Important notes
    
    RTL Simulation
    
    Synthesis (Synopsys DC)
    
    Place and Route
    
    Mini Ex
    
    Advanced
    Advanced
    
    Getting started
    
    Explore the library
    
    Post-synthesis simulation
    
    Post-synthesis simulation with timing
    
    Post-place-and-route sim
    
    Macro
    
    Through-Silicon-Via (TSV)
    
    OpenRAM
    
    Power estimation
    
    Clock-gating
    
    Temperature simulation
    
    Design: 🕸️ Network-on-Chip
    Design: 🕸️ Network-on-Chip
    
    Getting started
    
    Simulation
    
    SNN Simulation
    
    Synthesis
    
    Post-synthesis Simulation
    
    Place and Route
    
    Power estimation
    
    Sample projects
  - FPGA
    FPGA
    
    Basic
    Basic
    
    0. Installation
    
    Standalone RTL design
    Standalone RTL design
    
    1. Create a project
    
    2. Run the project on FPGA
    
    3. Understand the reports
    
    Simple SoC
    Simple SoC
    
    1. Create a project
    
    2. Port to SDK
    
    3. Run the program in the FPGA
    
    Custom IP
    Custom IP
    
    Introduction + Materials
    
    General Instruction
    
    Lab-1
    
    Lab-2
    
    Lab-3
    
    Lab-4
    
    Lab-5
    
    Sample Projects
    Sample Projects
    
    SNN on Basys 3
    
    SNN on Arty 7
    
    LIF neuron on MicroZed
- 🤖 Machine Learning
  🤖 Machine Learning
  - Getting started
  - General Machine Learning
    General Machine Learning
    
    Getting started
    
    Installation
    
    Dataset
    
    Notable techniques and Recommendation
  - Artificial Neural Network
  - Spiking Neural Network
    Spiking Neural Network
    
    Introduction
    
    Neurons
    
    Neurons
    
    Neuron
    
    Izhikevich
    
    SNNTorch
    SNNTorch
    
    Official tutorial
    
    Bindsnet
    Bindsnet
    
    STDP learning
    
    Spiking Jelly
    Spiking Jelly
    
    1.1 Time-step
    
    1.2 Using neuron
    
    1.3 Input size and net reset
    
    3.1 Revisit LIF neuron
    
    3.2 Revisit LIF neuron part 2
    
    3.3 Design your neuron
- Accessing servers
  Accessing servers
- 🎯 Optimization
  🎯 Optimization
  - Getting started
  - Single Objective
    Single Objective
    
    0-1 Knapsack
  - Multiple Objectives
    Multiple Objectives
    
    0-1 Knapsack
    
    MOO minicourse
- Makefile
  Makefile
- Git
  Git
  - Intro
  - Basic
  - Advanced
  - Branch
- Markdown
  Markdown
  - Intro
  - Basic
  - Advanced
♾️ Member
🎗️ Management
🎗️ Management
- 🔒 Password Protected
- 🖥️ Devices
- 🪑 Desk
- 📚 Books
- 🌐 Website
- 🖥 Server: how-to
- ⚗️ Materials
  ⚗️ Materials
- 🈸 University Docs
  🈸 University Docs
⚔️ Activities
⚔️ Activities
- Awards
- Contests
  Contests
  - All Contests
  - IEEE CAS Society Design Contest
    
    IEEE CAS Society Design Contest
  - LSI Contest
    
    LSI Contest
🌐 Links
🌐 Links
- 📝 The Thinking Circuit
- 🚧 Project
  🚧 Project
- 🌐 Useful link
- ↗️ Github
- ▶️ YouTube
📩 Contact

Table of contents

Verilog Coding Guidelines
- Wire/register/inout declarations follow this rule:
- Important notes

🏠 Docs
🗂️ Tutorial
🛠 HW Design
ASIC
Basic

Lt9DykkUQ02kc+0W3dxaBg==;cn29jPK5KMbh3YZcE2e/Itcu65VWb15EXd8C4omQzXwBKxzp6DJhvT8lrRYT8E29Gs0+uAevRPcMSBoT6/ZlnbzNgeOl8z4SXL7HZMBN9738Es2CNj1iYu5TQSMhXtDfl1YCokC+zmZ762ul9T5peYu/bUlz+8MMaMrZlKRucUWNSBd9pgneGMO7Zq7Of4EeT5NJJL0nPoLZMclEzVC9ngRsCohuqQIHdRjNL821PDeYwKuPZIskDCZggBTMxCszXIQ4vFRaKBaAI4m+TPlq8p28grFxustD90FEEihpC0O4/cmvUyrM7iWSqk3/lBB44ZpYU1pyeAjFCY6FXv5PrsFmJ3CKdW6CxSFV9uwzqdgcI+ym76aKMNnbT2R1MmxeB5q6hBEWMuaj55s/Yxuy8aUrAKrTHdwvp8+vc/RuYcPrnbDQkUuOUryidZFEi1ylLOpkzgeazdgVBqr/Csy1iqmyVgwdf+TVeiubuAxJaAZIcShQYFnPZA3UTSOdu/f46igcp/nM2PTDpLGR/H2xXkJ8ri72TuHC5ozHGx1GwB0m3ApZFBJjvvyPb9fMkWdE4S66u+NNDQ15JGZ8ozYWp/wesJa6CEyXkzrR4ZA9ED791WRSHSpZsF3vT6LilFsx/N+zwBb9VvnGyYYBUr3Y8TXqMExvdvVKP33jJgBpdQKvaLj2wF9FPc+LvRL3chtnafFwoG8gCYYGVAJOL/WnMHyCCxyY+WcE7/KKlzeo45DtqtkvnO9HdkE+MQtkk6ocrwNMWwnE57X7TX9i7KrGQudN4xuHLDYYBq8XH1pCgaWm7LGb3ooy8Ri9zcGA5C50W0O/LyVw6YZgr74b7P/0R5vDpLs43cuILF9Bfu6qIDo6OCbCurh8srCWacFOWl5iDg+wITVc9SvTPWhHrRl8rUBpRpTSDPLTjzTstzK4G8WqUzZLp/yXZztgAez7RrQFgX/zrUJLpP7a4P4k42/pcvzC/luIlXlbtUnBkB5K9/xismnIvi33/jX5PEm/9DOoZJFkQzpStGpPCSuMUwkIZJLyzbXQmsJlTSYFPqzsAh6L+/o4K4rDmSHS2ncsBgnI3MfUPX+PkFEpOpcoQjg/CBnz1cM5FdstAZrtsiaHCoLQ1Sk9w12p5XjdoV8enem8M9eygaS8tWDRFLVLlaEUhMv9SVppfXiwmty7oigphmohyAjwpjxr/I0FR85dozb3jVYACDmxaRD+IWCSC/urOLEkHc3D+gruP68+3rMtX3o7mT3N6vNAeRDYuEGiJXKikIjYTlU56cQshOoPLW+YVaTTAiAaIxTfFiLc1FEngSEE1lUz6LWJAnFdj+lgPgTD/rvc9Xu4HVpX6hfIyKtZ/+Tk8J4NCMs+BV/qczvOY+U7/A+sbfojS4R8c1Qcee13PGt7NuMT2Z2uGSpI5PJtF2iKC4KXE6K3Qpy/qllYK6tbevpM/teyaIwGkj26l1vdj6BRTzSd53r2HHiT9Z0crA1OnU+Yssj45qgNjL6adQk2+srwEbKMAzg5jQU4m2oo

㊙️ This website is password-protected and accessible to authorized members only.

Contact your administrator for access to this page.