E3Computing's Docs

Reset and Clock

👾 E3Computing HP
🏠 Docs
ℹ️ Information
ℹ️ Information
- 🌐 About this website
- 🔰 Guidance for new student (AY 2026)
- 🔰 Checklist for new student orientation meeting
  🔰 Checklist for new student orientation meeting
- 🚂 Training for new members
  🚂 Training for new members
- 🔬 Server/Page Info
  🔬 Server/Page Info
- 📑 Paper submission
  📑 Paper submission
- 🎓 Graduation Thesis
  🎓 Graduation Thesis
  - Preparation
  - After the presentation
👨‍🏫 Invited Talks
👨‍🏫 Invited Talks
📅 Meetings
📅 Meetings
🗂️ Tutorial
🗂️ Tutorial
- List of tutorials
- 🛠 HW Design
  🛠 HW Design
  - Verilog/SystemVerilog/VHDL tutorial
    Verilog/SystemVerilog/VHDL tutorial
    
    Intro
    
    Combinational Logic
    
    Sequential Logic
    
    Reset and Clock
    
    Naming
    
    RTL template
    
    Testbench template
    
    Useful website
    Useful website
    
    Asic-world
    
    Stitt-hub
    
    RTL-Training Repo
  - Simulate with Modelsim
    Simulate with Modelsim
    
    Introduction
    
    Clone the project
    
    Source the env variables
    
    Write your Verilog code
    
    Open Modelsim
    
    Use command line
    
    Code Coverage
    
    Write a script
    
    Learn More!
  - ASIC
    ASIC
    
    Basic
    Basic
    
    Getting started
    
    Writing Verilog
    
    RTL Simulation
    
    Synthesis (Synopsys DC)
    
    Place and Route
    
    Mini Ex
    
    Advanced
    Advanced
    
    Getting started
    
    Explore the library
    
    Post-synthesis simulation
    
    Post-synthesis simulation with timing
    
    Post-place-and-route sim
    
    Macro
    
    Through-Silicon-Via (TSV)
    
    OpenRAM
    
    Power estimation
    
    Clock-gating
    
    Temperature simulation
    
    Design: 🕸️ Network-on-Chip
    Design: 🕸️ Network-on-Chip
    
    Getting started
    
    Simulation
    
    SNN Simulation
    
    Synthesis
    
    Post-synthesis Simulation
    
    Place and Route
    
    Power estimation
    
    Sample projects
  - FPGA
    FPGA
    
    Basic
    Basic
    
    0. Installation
    
    Standalone RTL design
    Standalone RTL design
    
    1. Create a project
    
    2. Run the project on FPGA
    
    3. Understand the reports
    
    Simple SoC
    Simple SoC
    
    1. Create a project
    
    2. Port to SDK
    
    3. Run the program in the FPGA
    
    Custom IP
    Custom IP
    
    Introduction + Materials
    
    General Instruction
    
    Lab-1
    
    Lab-2
    
    Lab-3
    
    Lab-4
    
    Lab-5
    
    Sample Projects
    Sample Projects
    
    SNN on Basys 3
    
    SNN on Arty 7
    
    LIF neuron on MicroZed
- 🤖 Machine Learning
  🤖 Machine Learning
  - Getting started
  - General Machine Learning
    General Machine Learning
    
    Getting started
    
    Installation
    
    Dataset
    
    Notable techniques and Recommendation
  - Artificial Neural Network
  - Spiking Neural Network
    Spiking Neural Network
    
    Introduction
    
    Neurons
    
    Neurons
    
    Neuron
    
    Izhikevich
    
    SNNTorch
    SNNTorch
    
    Official tutorial
    
    Bindsnet
    Bindsnet
    
    STDP learning
    
    Spiking Jelly
    Spiking Jelly
    
    1.1 Time-step
    
    1.2 Using neuron
    
    1.3 Input size and net reset
    
    3.1 Revisit LIF neuron
    
    3.2 Revisit LIF neuron part 2
    
    3.3 Design your neuron
- Accessing servers
  Accessing servers
- 🎯 Optimization
  🎯 Optimization
  - Getting started
  - Single Objective
    Single Objective
    
    0-1 Knapsack
  - Multiple Objectives
    Multiple Objectives
    
    0-1 Knapsack
    
    MOO minicourse
- Makefile
  Makefile
- Git
  Git
  - Intro
  - Basic
  - Advanced
  - Branch
- Markdown
  Markdown
  - Intro
  - Basic
  - Advanced
♾️ Member
🎗️ Management
🎗️ Management
- 🔒 Password Protected
- 🖥️ Devices
- 🪑 Desk
- 📚 Books
- 🌐 Website
- 🖥 Server: how-to
- ⚗️ Materials
  ⚗️ Materials
- 🈸 University Docs
  🈸 University Docs
⚔️ Activities
⚔️ Activities
- Awards
- Contests
  Contests
  - All Contests
  - IEEE CAS Society Design Contest
    
    IEEE CAS Society Design Contest
  - LSI Contest
    
    LSI Contest
🌐 Links
🌐 Links
- 📝 The Thinking Circuit
- 🚧 Project
  🚧 Project
- 🌐 Useful link
- ↗️ Github
- ▶️ YouTube
📩 Contact

🏠 Docs
🗂️ Tutorial
🛠 HW Design
Verilog/SystemVerilog/VHDL tutorial

XG3WP+B6M7lmLsB39cAshQ==;GbLDcAv75mxerKNDJnUIfbCpxagu7aGGih03aja7E7/DE0LslTrt9NT4mPr4mDw9zwhFd8WVY+6WEbdyefjxFFesQavywpngXK8Z0XeoMQCwO5OSKP0g7KkFlsc3sUjruiJI0qyWNsIkIR1hTCrqZhccSzs+DuOtsrR9ZPUGtuSrJTB1asN6FkcGn+HsP4vIQQC4tcnir8KFRYMGtBI3HRVQUybXcJGMZyeGBMufffE0uyeLbUcI69ROasZ1FixiPsDqmJK2pIj1CTAw7SN5Nxm+Iq2U08/XfqzPAuarHb1E0W1P07WjLIdKI4EhMFfYnQjc+30SdiP4XAtfL4kQaD2nV4bTRHx5WXLqRCUgD1GEMHT7gnQ+Fts6XzMErF58ldsDKxI0QyZNAW1ZXsb5BOeUMWg++bHdIk6gtQI0HGNEuX7IA5GZbtLqrugaGLT0xBYxMfXOxXV94ImI/knHL1VJrXpgTwfES4jLQ6i28mYw9181QcVJ90AY4gJAVh9l2lMeqp4L4ExdU5rywON7y/qjRmc8ckptfhd1+e/4KyPeJyoqBoas/rq4wpKStgpaA9hdMwvIdwVQF7HYn/yOsOfLzLiSeWzB34I96XD5lIhbbZDtM8pYPHlhzODpAtlBcQvoljBZjuT7/4acI9cRDZc0Z80SPrKQVQYBngdK1jPQ8vt5jWUYGuXgRyz6X1M4yiEV0+xkefn79pa3CAtUM9RvlFR/QWJY6R9WQ3pKzD4oKB8yX4VNYd2hrvOm+37BbE94FkiA3wzmNNenvRJO6OMxbp+8NDj7SAQhVfC0rs5ardAY2KDf0NWzvnYGzZSiOLJmi13Z7qooYxifsg4mtkpXGJCwPh+20x3MjTgXwTAsJ2HnpHcvPOlKsE4potWH

㊙️ This website is password-protected and accessible to authorized members only.

Contact your administrator for access to this page.