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E3Computing's Docs
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  • πŸ‘Ύ E3Computing HP
  • 🏠 Docs
    • 🌐 About this website
    • πŸ”° Guidance for new student (AY 2026)
    • πŸ”° Checklist for new student orientation meeting
      • New member: Week 1/2
      • New member: HW Week 3/4/5
      • New member: SW Week 3/4/5
      • πŸ–₯️ Devices
      • Printer/Scanner
      • Updating this website
      • Research Paper Writing 1
      • Guidelines
      • Paper Preparation
      • What to submit (journal)
      • What to submit (conference)
      • Suggested List
      • After Review
      • After Acceptance
      • Slides preparation
      • Preparation
      • After the presentation
  • πŸ‘¨β€πŸ« Invited Talks
    • Meeting Schedule
    • Group Meeting
    • 1-on-1 Meeting
    • ASL: RPR/RPS
    • Master: Research Plan/Progress Seminar
    • PhD: Research Progress Seminar
    • List of tutorials
        • Intro
        • Combinational Logic
        • Sequential Logic
        • Reset and Clock
        • Naming
        • RTL template
        • Testbench template
          • Asic-world
          • Stitt-hub
          • RTL-Training Repo
        • Introduction
        • Clone the project
        • Source the env variables
        • Write your Verilog code
        • Open Modelsim
        • Use command line
        • Code Coverage
        • Write a script
        • Learn More!
          • Getting started
          • Writing Verilog
          • RTL Simulation
          • Synthesis (Synopsys DC)
          • Place and Route
          • Mini Ex
          • Getting started
          • Explore the library
          • Post-synthesis simulation
          • Post-synthesis simulation with timing
          • Post-place-and-route sim
          • Macro
          • Through-Silicon-Via (TSV)
          • OpenRAM
          • Power estimation
          • Clock-gating
          • Temperature simulation
          • Getting started
          • Simulation
          • SNN Simulation
          • Synthesis
          • Post-synthesis Simulation
          • Place and Route
          • Power estimation
        • Sample projects
          • 0. Installation
          • 1. Create a project
          • 2. Run the project on FPGA
          • 3. Understand the reports
          • 1. Create a project
          • 2. Port to SDK
          • 3. Run the program in the FPGA
          • Introduction + Materials
          • General Instruction
          • Lab-1
          • Lab-2
          • Lab-3
          • Lab-4
          • Lab-5
            • SNN on Basys 3
            • SNN on Arty 7
            • LIF neuron on MicroZed
      • Getting started
        • Getting started
        • Installation
        • Dataset
        • Notable techniques and Recommendation
      • Artificial Neural Network
        • Introduction
        • Neurons
          • Neuron
          • Izhikevich
          • Official tutorial
          • STDP learning
          • 1.1 Time-step
          • 1.2 Using neuron
          • 1.3 Input size and net reset
          • 3.1 Revisit LIF neuron
          • 3.2 Revisit LIF neuron part 2
          • 3.3 Design your neuron
      • Intro
      • SSH
      • SAMBA
      • SFTP
      • Installing Python
      • Installing Pytorch
      • Github
      • X11 Forwarding
      • Login without entering password
      • Tailscale+VNC
      • Running Tools
      • Getting started
        • 0-1 Knapsack
        • 0-1 Knapsack
        • MOO minicourse
      • Introduction
      • Write a simple Makefile
      • Execute Makefile
      • Learn more about Makefile
      • Intro
      • Basic
      • Advanced
      • Branch
      • Intro
      • Basic
      • Advanced
  • ♾️ Member
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    • βš—οΈ Materials
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      • πŸ’° Funding for Travel
      • πŸ’΅ Journal APC
    • Awards
      • All Contests
      • IEEE CAS Society Design Contest
      • LSI Contest
    • πŸ“ The Thinking Circuit
      • List of Project
      • Torch2HW
      • πŸŽ“ Available GT Topics (2024)
    • 🌐 Useful link
    • ↗️ Github
    • ▢️ YouTube
  • πŸ“© Contact
  1. 🏠 Docs
  2. πŸ—‚οΈ Tutorial
  3. πŸ›  HW Design
  4. ASIC
  5. Advanced
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