E3Computing's Docs

Execute Makefile

👾 E3Computing HP
🏠 Docs
ℹ️ Information
ℹ️ Information
- 🌐 About this website
- 🔰 Guidance for new student (AY 2026)
- 🔰 Checklist for new student orientation meeting
  🔰 Checklist for new student orientation meeting
- 🚂 Training for new members
  🚂 Training for new members
- 🔬 Server/Page Info
  🔬 Server/Page Info
- 📑 Paper submission
  📑 Paper submission
- 🎓 Graduation Thesis
  🎓 Graduation Thesis
  - Preparation
  - After the presentation
👨‍🏫 Invited Talks
👨‍🏫 Invited Talks
📅 Meetings
📅 Meetings
🗂️ Tutorial
🗂️ Tutorial
- List of tutorials
- 🛠 HW Design
  🛠 HW Design
  - Verilog/SystemVerilog/VHDL tutorial
    Verilog/SystemVerilog/VHDL tutorial
    
    Intro
    
    Combinational Logic
    
    Sequential Logic
    
    Reset and Clock
    
    Naming
    
    RTL template
    
    Testbench template
    
    Useful website
    Useful website
    
    Asic-world
    
    Stitt-hub
    
    RTL-Training Repo
  - Simulate with Modelsim
    Simulate with Modelsim
    
    Introduction
    
    Clone the project
    
    Source the env variables
    
    Write your Verilog code
    
    Open Modelsim
    
    Use command line
    
    Code Coverage
    
    Write a script
    
    Learn More!
  - ASIC
    ASIC
    
    Basic
    Basic
    
    Getting started
    
    Writing Verilog
    
    RTL Simulation
    
    Synthesis (Synopsys DC)
    
    Place and Route
    
    Mini Ex
    
    Advanced
    Advanced
    
    Getting started
    
    Explore the library
    
    Post-synthesis simulation
    
    Post-synthesis simulation with timing
    
    Post-place-and-route sim
    
    Macro
    
    Through-Silicon-Via (TSV)
    
    OpenRAM
    
    Power estimation
    
    Clock-gating
    
    Temperature simulation
    
    Design: 🕸️ Network-on-Chip
    Design: 🕸️ Network-on-Chip
    
    Getting started
    
    Simulation
    
    SNN Simulation
    
    Synthesis
    
    Post-synthesis Simulation
    
    Place and Route
    
    Power estimation
    
    Sample projects
  - FPGA
    FPGA
    
    Basic
    Basic
    
    0. Installation
    
    Standalone RTL design
    Standalone RTL design
    
    1. Create a project
    
    2. Run the project on FPGA
    
    3. Understand the reports
    
    Simple SoC
    Simple SoC
    
    1. Create a project
    
    2. Port to SDK
    
    3. Run the program in the FPGA
    
    Custom IP
    Custom IP
    
    Introduction + Materials
    
    General Instruction
    
    Lab-1
    
    Lab-2
    
    Lab-3
    
    Lab-4
    
    Lab-5
    
    Sample Projects
    Sample Projects
    
    SNN on Basys 3
    
    SNN on Arty 7
    
    LIF neuron on MicroZed
- 🤖 Machine Learning
  🤖 Machine Learning
  - Getting started
  - General Machine Learning
    General Machine Learning
    
    Getting started
    
    Installation
    
    Dataset
    
    Notable techniques and Recommendation
  - Artificial Neural Network
  - Spiking Neural Network
    Spiking Neural Network
    
    Introduction
    
    Neurons
    
    Neurons
    
    Neuron
    
    Izhikevich
    
    SNNTorch
    SNNTorch
    
    Official tutorial
    
    Bindsnet
    Bindsnet
    
    STDP learning
    
    Spiking Jelly
    Spiking Jelly
    
    1.1 Time-step
    
    1.2 Using neuron
    
    1.3 Input size and net reset
    
    3.1 Revisit LIF neuron
    
    3.2 Revisit LIF neuron part 2
    
    3.3 Design your neuron
- Accessing servers
  Accessing servers
- 🎯 Optimization
  🎯 Optimization
  - Getting started
  - Single Objective
    Single Objective
    
    0-1 Knapsack
  - Multiple Objectives
    Multiple Objectives
    
    0-1 Knapsack
    
    MOO minicourse
- Makefile
  Makefile
  - Introduction
  - Write a simple Makefile
  - Execute Makefile Execute Makefile
    Table of contents
    
    make with different Makefile name
  - Learn more about Makefile
- Git
  Git
  - Intro
  - Basic
  - Advanced
  - Branch
- Markdown
  Markdown
  - Intro
  - Basic
  - Advanced
♾️ Member
🎗️ Management
🎗️ Management
- 🔒 Password Protected
- 🖥️ Devices
- 🪑 Desk
- 📚 Books
- 🌐 Website
- 🖥 Server: how-to
- ⚗️ Materials
  ⚗️ Materials
- 🈸 University Docs
  🈸 University Docs
⚔️ Activities
⚔️ Activities
- Awards
- Contests
  Contests
  - All Contests
  - IEEE CAS Society Design Contest
    
    IEEE CAS Society Design Contest
  - LSI Contest
    
    LSI Contest
🌐 Links
🌐 Links
- 📝 The Thinking Circuit
- 🚧 Project
  🚧 Project
- 🌐 Useful link
- ↗️ Github
- ▶️ YouTube
📩 Contact

Table of contents

make with different Makefile name

ba1w4YgO5KflgPSwrdswyA==;Z/tIJr57DcW8DuVUtrhe21LdAgB4sp1xFvizSeylRJaHQu3gF0xqK2VqKFC91ox3PqItJnRGNVKhAr8iIdOnuBeeH3sGyNhtaDDo0suKlfmEZQon+Y2QN6loIAY2m2FePC432izr/os9JI2PrxtNwveMxpSIkK0WHSuN4BJL5RabVpfUat4gHrcD2roGT9BFkbdhwNav3JYBTkcUN4yZgcrTg7kCQBfdXd5AiHnpT3vHAZrgrhLs9sxjC4cSPPCzOHHelzZZI/7b/W5rjKv8X3yVy8V+93smzYiO2EJvAAXLF1UiwKyxCGB3TrPPv8yZYCjaOTZWpU7i7nWTLMJX4ZVTsYeXMKmBdBN291A1DKI6MTjKZr6mOtDqebdsA6TCdZX5sgomc+QfBufpfxegRV3g0ucT7JefpCqoB1CTdGp78IcmCpBEqSGoLjEtWemnMYWGQJS/8OJLTWT5GJ4ygdO6Gs4D2JD26g3b54eOWFKUtxIObyG/oIvsI+/K0l86fVMx6RbQG4EjU/DYtkLmatWNTHQFsWceOr/hklkHt+jGUFWFeAdTriDvkCiOigf3kqrYHCAHyf/VkR7ogI2V2bxb+phn8btcqat75QtXrGUujQqkZwlVfoqe0NE1/WFKDLvgBEJgftf4cL7PJ5/ueoTGIR+4+7Cgn3y6cOr5v33bugdqrO6UeQxu66iC8U4CB4WhrQbf4e3VfLgKcGJNl2QcymeVHgj0HjGt9nIiuRXgd6wb+GSfwyvXm+0PMVV/7tf/garJ8I3PYf1CaGF+9j/U8RL4OQo2/4t6u40OtyMMFY4tDaERKnFanN2XPLydYkTN8AjlL9w2OOvQBKqJD3PAlNPHp4iaQmMq6wXFKGlUeIZc/7Qbdm+6THM3rgwGx/VU9iq5VMBSBLTAPkBF2F7DruSgJLc2/Grnd6BL7MxxxrveneTABUy3LhPFmF9RGPQ2e6EeTtPBO6AE5F8trWZzDuPvQyViAqCMDZQ72m8aI04kMKa152yfwK2zLfjLgmB0Bo+QoBm6BZHe074oPGCgkSmbsReUUWc3lwyN+WkWYEPJ6ARzgUYnaKi4NNY9MgIM0oe3qCEHd38MJ6Jk03XNGSatWG2eIBhvC4CJXGIHeUqomLH7ZOYQHiq4ebePRNl5afhVVNLz2DwQLfvyi8AnZjc0bAjweeFgik8uUB3DKZ0YqEMKayP+FKwbnkjkjcdYNFj+bYcXoyRzEesgjhCwxHEDnBwlX0ZbKR6d0j52Ciqo9JbrCBxWUMmruSyw

㊙️ This website is password-protected and accessible to authorized members only.

Contact your administrator for access to this page.