Internal Docs @ E3 Computing Group

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ℹ️ Information
ℹ️ Information
- 🌐 About this website
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- 🔰 Checklist for new student orientation meeting
  🔰 Checklist for new student orientation meeting
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🗂️ Tutorial
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- List of tutorials
- 🛠 HW Design
  🛠 HW Design
  - Verilog/SystemVerilog/VHDL tutorial
    Verilog/SystemVerilog/VHDL tutorial
    
    Intro
    
    Combinational Logic
    
    Sequential Logic
    
    Reset and Clock
    
    Naming
    
    RTL template
    
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    Useful website
    Useful website
    
    Asic-world
    
    Stitt-hub
    
    RTL-Training Repo
  - Simulate with Modelsim
    Simulate with Modelsim
    
    Introduction
    
    Clone the project
    
    Source the env variables
    
    Write your Verilog code
    
    Open Modelsim
    
    Use command line
    
    Code Coverage
    
    Write a script
    
    Learn More!
  - ASIC
    ASIC
    
    Basic
    Basic
    
    Getting started
    
    Writing Verilog
    
    RTL Simulation
    
    Synthesis (Synopsys DC)
    
    Place and Route
    
    Mini Ex
    
    Advanced
    Advanced
    
    Getting started
    
    Explore the library
    
    Post-synthesis simulation
    
    Post-synthesis simulation with timing
    
    Post-place-and-route sim
    
    Macro
    
    Through-Silicon-Via (TSV)
    
    OpenRAM
    
    Power estimation
    
    Clock-gating
    
    Temperature simulation
    
    Design: 🕸️ Network-on-Chip
    Design: 🕸️ Network-on-Chip
    
    Getting started
    
    Simulation
    
    SNN Simulation
    
    Synthesis
    
    Post-synthesis Simulation
    
    Place and Route
    
    Power estimation
    
    Sample projects
  - FPGA
    FPGA
    
    Basic
    Basic
    
    0. Installation
    
    Standalone RTL design
    Standalone RTL design
    
    1. Create a project
    
    2. Run the project on FPGA
    
    3. Understand the reports
    
    Simple SoC
    Simple SoC
    
    1. Create a project
    
    2. Port to SDK
    
    3. Run the program in the FPGA
    
    Custom IP
    Custom IP
    
    Introduction + Materials
    
    General Instruction
    
    Lab-1
    
    Lab-2
    
    Lab-3
    
    Lab-4
    
    Lab-5
    
    Sample Projects
    Sample Projects
    
    SNN on Basys 3
    
    SNN on Arty 7
    
    LIF neuron on MicroZed
- 🤖 Machine Learning
  🤖 Machine Learning
  - Getting started
  - General Machine Learning
    General Machine Learning
    
    Getting started
    
    Installation
    
    Dataset
    
    Notable techniques and Recommendation
  - Artificial Neural Network
  - Spiking Neural Network
    Spiking Neural Network
    
    Introduction
    
    Neurons
    
    Neurons
    
    Neuron
    
    Izhikevich
    
    SNNTorch
    SNNTorch
    
    Official tutorial
    
    Bindsnet
    Bindsnet
    
    STDP learning
    
    Spiking Jelly
    Spiking Jelly
    
    1.1 Time-step
    
    1.2 Using neuron
    
    1.3 Input size and net reset
    
    3.1 Revisit LIF neuron
    
    3.2 Revisit LIF neuron part 2
    
    3.3 Design your neuron
- Accessing servers
  Accessing servers
- 🎯 Optimization
  🎯 Optimization
  - Getting started
  - Single Objective
    Single Objective
    
    0-1 Knapsack
  - Multiple Objectives
    Multiple Objectives
    
    0-1 Knapsack
    
    MOO minicourse
- Makefile
  Makefile
- Git
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  - Intro
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🌐 Links
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📩 Contact

Table of contents

Current Projects
Archived Projects

EwdNe0TTMsfFlbWN4GWBCg==;ekMbZnAEOGN3MGpvs6eOhe88lIgKpuwNlNULhUUvc213Igsg/t8+XUhGA9/Jm9Zy32fH6w57Po/tFx/yHqtrCxATCsgdISZ8MrJrjYRKeaXdbs/p99GPg/xqxo6wgInQvuZsMysmP/2oVntC8XhPzIJguIbsQhY3iUkRWQUJd6uoo8ODhRg8uWqRh+a/I5LcCWidiph7XBjJfxfHIrvtuq3xf6XeqEglAKlfSwynBsvQejrWfa+jE2LRITVO1wHndg5Ic5QjC4UwxP9d8mi886TRow82Vc3uUIP1Bz61H3OIaXrzuXJK7+a4nYJYJrakDj4Ke9oBvvvOOSvQBALCmmx2a6kb7qMwawij4nntnHkKT6O9edi3Pa+Z35NuBsujl3y9T1QRxannPiVxyEfB9Nz+s2UC5oQrxfGoSmzXPyt0x/itoz559lGlx5rL8eCDn8qWtwz7W0G2dPD2VmeUkzHgmPWWO5x6p+QYGAVSrdz0DNB9Ef71ln4tYg5viVus8VogIegq2ebTtKV2z4p1XJqgJ0HMfRNMsyaaKmpd6CIErDmQnIIwum8Gf7ZhNaMJknBMaxG1Vz5pP2kmh0TMo2K9Z+EcE/NVVkOL3w7v9lT1bwvkKws8LExOZPQScG2RhV3EBcAQ+nz3CcqwNMYgHyG8C6kAz9pkB/9Sp0w3/0Y=

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